Final Testbench

Gün 7: Bitirme Projesi - Bölüm 2 | Tüm bileşenleri bir araya getiren son testbench

Kaynak Kod

// =============================================================================
// GUN 7 - Konu 6: Final Testbench Top-Level
// =============================================================================
// Tum bilesenleri bir araya getiren son testbench.
// Derleme: Tum dosyalari birlikte derleyin.
//   Ornek (Questa/ModelSim):
//     vlog design.v 6_1_alu_interface.sv 6_2_transaction.sv 6_3_generator.sv
//          6_4_driver.sv 7_1_monitor.sv 7_2_scoreboard.sv 7_5_coverage.sv
//          7_3_environment.sv 7_4_test.sv 7_6_testbench_top_final.sv
//     vsim tb_top_final
// =============================================================================

`include "6_2_transaction.sv"
`include "6_3_generator.sv"
`include "6_4_driver.sv"
`include "7_1_monitor.sv"
`include "7_2_scoreboard.sv"
`include "7_5_coverage.sv"
`include "7_3_environment.sv"
`include "7_4_test.sv"

module tb_top_final;

  // Saat uretimi
  logic clk = 0;
  always #5 clk = ~clk;  // 100MHz (periyot = 10ns)

  // Interface
  alu_if aif(clk);

  // DUT (Design Under Test)
  alu dut (
    .clk       (aif.clk),
    .rst_n     (aif.rst_n),
    .in_valid  (aif.in_valid),
    .operand_a (aif.operand_a),
    .operand_b (aif.operand_b),
    .opcode    (aif.opcode),
    .out_valid (aif.out_valid),
    .result    (aif.result),
    .flags     (aif.flags)
  );

  // Test secimi
  initial begin
    ALU_Base_Test test;
    string test_name;

    // Komut satirindan test secimi: +TEST=Random_Test
    if (!$value$plusargs("TEST=%s", test_name))
      test_name = "Random_Test";  // Varsayilan

    $display("============================================================");
    $display("  ALU DOGRULAMA PROJESI - BITIRME");
    $display("  Secilen Test: %s", test_name);
    $display("============================================================");

    case (test_name)
      "Random_Test":   test = new ALU_Random_Test(aif, aif);
      "Corner_Test":   test = new ALU_Corner_Test(aif, aif);
      "Add_Stress":    test = new ALU_Add_Stress_Test(aif, aif);
      default: begin
        $display("  Bilinmeyen test: %s, Random_Test kullaniliyor", test_name);
        test = new ALU_Random_Test(aif, aif);
      end
    endcase

    test.run();

    $display("\n============================================================");
    $display("  SIMULASYON TAMAMLANDI");
    $display("============================================================");
    $finish;
  end

  // VCD dalga formu
  initial begin
    $dumpfile("alu_tb_final.vcd");
    $dumpvars(0, tb_top_final);
  end

endmodule