ALU Interface Tanımı

Gün 6: Bitirme Projesi - Bölüm 1 | Bitirme projesi: ALU interface ve clocking block

Kaynak Kod

// =============================================================================
// GUN 6 - Konu 1: ALU Interface ve Clocking Block Tanimlamalari
// =============================================================================

interface alu_if(input logic clk);
  // Sinyaller
  logic        rst_n;
  logic        in_valid;
  logic [7:0]  operand_a;
  logic [7:0]  operand_b;
  logic [2:0]  opcode;
  logic        out_valid;
  logic [15:0] result;
  logic [3:0]  flags;

  // Testbench clocking block
  clocking drv_cb @(posedge clk);
    default input #1 output #1;
    output in_valid, operand_a, operand_b, opcode;
    input  out_valid, result, flags;
  endclocking

  // Monitor clocking block (sadece okuma)
  clocking mon_cb @(posedge clk);
    default input #1;
    input in_valid, operand_a, operand_b, opcode;
    input out_valid, result, flags;
  endclocking

  // Modport'lar
  modport driver  (clocking drv_cb, output rst_n, input clk);
  modport monitor (clocking mon_cb, input clk, rst_n);
  modport dut (
    input  clk, rst_n, in_valid, operand_a, operand_b, opcode,
    output out_valid, result, flags
  );
endinterface